Field of the Invention
The present invention relates to a bus system having a bus, a number of units that can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated the bus.
Bus systems such as these have been known in many different embodiments for many years.
Reference is had to FIG. 1, which shows the basic design of such a bus system. The system shown in FIG. 1 comprises a bus, identified with the reference symbol BUS; three exemplary units CPU1, CPU2, and RAM, each connected to the bus BUS and connectible to one another via the bus BUS; and a bus controller BUS CTRL connected to the bus and configured to control bus allocation.
In the exemplary prior system, the bus BUS is the internal bus of a microcontroller. The units CPU1 and CPU2 are different cores of the microcontroller. Further, the unit RAM is a memory that can be accessed both by the first core CPU1 and by the second core CPU2.
Of the units CPU1, CPU2, and RAM, the units CPU1 and CPU2 are master units (i.e., units which request the bus and can then become the bus master). The unit RAM is a slave unit (i.e., a unit which may only be a bus slave).
The bus controller BUS CTRL defines which of the existing master units CPU1 and CPU2 may be the bus master 1, when and for how long. The master units CPU1 and CPU2 are for this purpose each connected to the bus controller BUS CTRL via lines REQUEST and GRANT. When one master unit requires the bus BUS in order to output data to one of the other units connected to the bus, or to request data from another unit, it signals this to the bus controller BUS CTRL by outputting an appropriate signal via the line REQUEST. The bus controller then checks whether the bus is free and uses the line GRANT to report to the unit which is requesting the bus that it can use the bus (if the bus is free) or that it cannot use the bus at the moment (if another unit is currently the bus master).
One known problem with such bus systems is that units which have to output data or urgently require data from another unit sometimes have to wait for a very long time before they can be allocated to the bus BUS.